Control method and circuit with indirect input voltage detection by switching current slope detection

ABSTRACT

The present invention provides a method and a control circuit to detect an input voltage for the control and protections of a power converter. It includes a current sense circuit for generating a current signal in response to a switching current of a transformer. A detection circuit is coupled to sense the current signal for generating a slope signal in response to a slope of the current signal. A protection circuit is further developed to control the switching signal in accordance with the slope signal. The level of the slope signal is corrected correlated to the input voltage of the power converter.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power converters, and more specificallyrelates to the control of switching power converters.

2. Description of Related Art

Switching power converters have been widely used to provide regulatedvoltage and current. A transformer (an inductive device) is used in thepower converter for energy store and power transfer. FIG. 1 shows acircuit schematic of a traditional power converter. A controller 15generates a switching signal S_(W) at an output terminal OUT to regulatethe output of the power converter in response to a feedback signalV_(FB). In general, the feedback signal V_(FB) is obtained at a feedbackterminal FB of the controller 15 by detecting the output voltage V_(O)of the power converter through an optical-coupler or a feedback circuitincluding an auxiliary winding (Figure not shown).

The switching signal S_(W) drives a power transistor 12 for switching atransformer 10. The transformer 10 is connected to an input voltageV_(IN) of the power converter. The energy of the transformer 10 istransferred to the output voltage V_(O) of the power converter through arectifier 17 and a capacitor 18. A resistor R_(S) is connected seriallywith the power transistor 12 to generate a current signal V_(I) inresponse to a switching current I_(P) of the transformer 10. The currentsignal V_(I) is coupled to a current-sense terminal VS of the controller15 for the control and protections of the power converter. A resistor 19is further connected from the input voltage V_(IN) to an input terminalIN of the controller 15 for over-voltage and under-voltage protections,etc.

Furthermore, the over-power protection of power converter requiressensing the input voltage V_(IN) to control the maximum output power asa constant. The approach was disclosed as “PWM controller forcontrolling output power limit of a power supply” by Yang et al., U.S.Pat. No. 6,611,439. The drawback of this prior art is the power losscaused by the resistor 19 especially when the input voltage V_(IN) ishigh. The object of the present invention is to sense the input voltageV_(IN) for the control and protections without the need of the resistor19 for saving power. Moreover, reducing input terminals of thecontroller 15 is another object of the present invention.

SUMMARY OF THE INVENTION

The present invention provides a method and a control circuit to detectan input voltage for the control and protections of a power converter.It includes a current sense circuit to generate a current signal inresponse to a switching current of a transformer. The transformer isoperated as an inductive device. A detection circuit is coupled to sensethe current signal for generating a slope signal in response to a slopeof the current signal. When a power transistor of the power converter isturned on, the detection circuit will sample the current signal during afirst period to generate a first signal. After that, sampling thecurrent signal during a second period will generate a second signal. Theslope of the current signal is determined in accordance with the firstsignal and the second signal. A protection circuit is further utilizedto control the switching signal in accordance with the slope signal. Thelevel of the slope signal is corrected correlated to the input voltageof the power converter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide further understandingof the invention, and are incorporated into and constitute a part ofthis specification. The drawings illustrate embodiments of the inventionand, together with the description, serve to explain the principles ofthe invention.

FIG. 1 shows a circuit diagram of a traditional power converter having aresistor coupled to detect the input voltage of the power converter.

FIG. 2 shows a circuit diagram of a preferred control circuit of a powerconverter according to the present invention.

FIG. 3 shows switching current waveforms according to the presentinvention.

FIG. 4 shows a circuit diagram of a preferred embodiment of a switchingcontroller according to the present invention.

FIG. 5 shows a circuit diagram of a preferred embodiment of anoscillation circuit according to the present invention.

FIG. 6 shows a circuit diagram of a preferred embodiment of aV_(IN)-circuit according to the present invention.

FIG. 7 shows a circuit diagram of a preferred embodiment of a detectioncircuit according to the present invention.

FIG. 8 shows a circuit schematic of a preferred embodiment of a pulsegenerator according to the present invention.

FIG. 9 shows signal-waveforms of the switching controller according tothe present invention.

FIG. 10 shows the circuit diagram of a preferred embodiment of a V_(IN)signal generator and a protection signal generator according to thepresent invention.

FIG. 11 shows a circuit schematic of a preferred embodiment of ablanking circuit according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows a circuit diagram of a preferred control circuit of a powerconverter. The power converter includes a power transistor 20, atransformer 30, a rectifier 40, a capacitor 45, a switching controller50 and a resistor R_(S). The transformer 30 serves as an inductancedevice coupled to receive an input voltage V_(IN). The power transistor20 is connected serially with the transformer 30 to switch thetransformer 30. The resistor R_(S) serves as a current sense circuitconnected to the power transistor 20 to develop a current signal V_(I)in response to a switching current I_(P) of the transformer 30. Thecurrent signal V_(I) represents the switching current I_(P). The currentsignal V_(I) is coupled to a current-sense terminal VS of the switchingcontroller 50 for the control and protections of the power converter. Anoutput terminal OUT of the switching controller 50 generates a switchingsignal S_(W) to control the power transistor 20 for regulating theoutput of the power converter in response to the current signal V_(I)and a feedback signal V_(FB). The feedback signal V_(FB) is generated ata feedback terminal FB of the switching circuit 50 for the feedbackregulation in response to the output of the power converter. The energyof the transformer 30 is transferred to the output voltage V_(O) of thepower converter through the rectifier 40 and the capacitor 45.

The switching controller 50 detects the input voltage V_(IN) for theprotections of the power converter. The input voltage V_(IN) is detectedby sensing a slope of the switching current I_(P). FIG. 3 showsswitching current waveforms. The slope of the switching current I_(P) isproduced in response to the level of the input voltage V_(IN). Forexample, the slopes 31, 32 and 33 are generated in response to the inputvoltages V_(IN1), V_(IN2) and V_(IN3) respectively. The level of theinput voltage is V_(IN)>V_(IN2)>V_(IN3). Once the switching signal S_(W)is turned on, the switching current I_(P) is generated accordantly,

$\begin{matrix}{I_{P} = {\frac{V_{IN}}{L_{P}} \times T_{ON}}} & (1)\end{matrix}$

$\begin{matrix}{V_{IN} = \frac{\Delta\; I \times L_{P}}{\Delta T}} & (2)\end{matrix}$

where L_(P) is the inductance of the primary winding of the transformer30; T_(ON) is on time of the switching signal S_(W).

FIG. 4 shows a circuit diagram of the switching controller 50. Itincludes a switching circuit 60 to generate the switching signal S_(W)in response to an oscillation signal IPS. An oscillation circuit 100 isdeveloped to generate the oscillation signal IPS and the timing signalsS₁, S₂. Timing signals S₁ and S₂ serve as sample signals outputted to aV_(IN)-circuit 200. The V_(IN)-circuit 200 is coupled to receive thecurrent signal V_(I) for producing an input-voltage signal V_(V) (shownin FIG. 10) in accordance with the slope of the current signal V_(I).Meanwhile, the V_(IN)-circuit 200 generates a control signal ENB, acurrent-limit signal V_(M) and a blanking adjustment signal V_(B) inresponse to the input-voltage signal V_(V) for power converterprotections.

The switching circuit 60 includes a flip-flop 70 to generate theswitching signal S_(W) through an AND gate 75. The input terminal of theAND gate 75 is connected to the output terminal Q of the flip-flop 70.Another input terminal of the AND gate 75 is connected to theoscillation circuit 100 to receive the oscillation signal IPS to limitthe maximum on time of the switching signal S_(W). The input terminal Dof the flip-flop 70 is coupled to the V_(IN)-circuit 200 to receive thecontrol signal ENB. The flip-flop 70 is enabled in response to theoscillation signal IPS coupled to the clock input terminal CK of theflip-flop 70 if the control signal ENB is enabled.

The switching signal S_(W) is coupled to a blanking circuit 80 togenerate a blanking signal S_(K) in response to the switching signalS_(W). The blanking signal S_(K) ensures a minimum on time of theswitching signal S_(W) when the switching signal S_(W) is enabled. Theblanking adjustment signal V_(B) is coupled to the blanking circuit 80to adjust the blanking time of the blanking signal S_(K). Therefore, theblanking time of the blanking signal S_(K) will be increased in responseto the decrease of the input voltage V_(IN).

The blanking signal S_(K) is connected to the input terminal of an NANDgate 66. The output terminal of the NAND gate 66 is coupled to the resetterminal R of the flip-flop 70 to reset the flip-flop 70. Another inputterminal of the NAND gate 66 is connected to the output terminal of anNAND gate 65. The input terminal of the NAND gate 65 is connected to theoutput terminal of a comparator 62. Another input terminal of the NANDgate 65 is connected to the output terminal of a comparator 63. Thecomparator 62 is utilized to limit the maximum switching current I_(P).The positive input terminal of the comparator 62 is connected to theV_(IN)-circuit 200 to receive the current-limit signal V_(M). Thenegative input terminal of the comparator 62 and the negative inputterminal of the comparator 63 are coupled to receive the current signalV_(I). The positive input terminal of the comparator 63 is coupled toreceive the feedback signal V_(FB) for the feedback loop control.

FIG. 5 shows the circuit diagram of the oscillation circuit 100. Acharge current 110 is coupled to a supply voltage V_(CC). The chargecurrent 110 is serially connected with a switch 115 for charging acapacitor 130. A discharge current 120 is coupled to the ground. Thedischarge current 120 is serially connected with a switch 125 fordischarging the capacitor 130. A ramp signal RAMP is therefore producedon the capacitor 130. Comparators 150, 151, NAND gates 155, 156 and aninverter 158 are used to generate the oscillation signal IPS to controlthe switch 115. The oscillation signal IPS is further utilized tocontrol the switch 125 through an inverter 159. The oscillation signalIPS is further transmitted to the V_(IN)-circuit 200 and the switchingcircuit 60 respectively (shown in FIG. 4). The ramp signal RAMP iscoupled to the negative input terminal of the comparator 150 and thepositive input terminal of the comparator 151 respectively. Trip-pointvoltages V_(H) and V_(L) are connected to the positive input terminal ofthe comparators 150 and the negative input terminal of the comparator151 respectively. The ramp signal RAMP is thus swing in between thetrip-point voltages V_(H) and V_(L).

The input terminal of the NAND gate 155 is coupled to the outputterminal of the comparator 150. The input terminal of the NAND gate 156is coupled to the output terminal of the comparator 151. Another inputterminal of the NAND gate 156 is coupled to the output terminal of theNAND gate 155. The output terminal of the NAND gate 156 is coupled toanother input terminal of the NAND gate 155. The output terminal of theNAND gate 155 is coupled to the input terminal of the inverter 158. Theoscillation signal IPS is generated by the output terminal of theinverter 158. The output terminal of the inverter 158 is further coupledto the input terminal of the inverter 159 to receive the oscillationsignal IPS. The inverter 159 inverts the oscillation signal IPS tocontrol the switch 125.

The negative input terminals of the comparators 160 and 170 are coupledto receive the ramp signal RAMP for generating the timing signals S₁ andS₂. Threshold voltages V₁ and V₂ are connected to the positive inputterminals of the comparators 160 and 170 respectively. The level of thevoltage is V_(H)>V₂>V_(I)>V_(L). The output terminal of the comparator160 is connected to the input terminal of an AND gate 165 to generatethe first timing signal S₁. The output of the comparator 170 isconnected to the input terminal of an AND gate 175 to generate thesecond timing signal S₂. The input terminals of the comparators 165 and175 are further connected to receive the oscillation signal IPS and theswitching signal S_(W). Since the oscillation signal IPS is coupled toenable the switching signal S_(W) and turn on the power transistor 20(shown in FIG. 2) , the first timing signal S₁ is generated during afirst period T₁ (shown in FIG. 9) when the power transistor 20 is turnedon. The second timing signal S₂ is produced during a second period T₂(shown in FIG. 9) when the power transistor 20 is turned on. The firsttiming signal S₁ and the second timing signal S₂ are synchronized withthe oscillation signal IPS.

FIG. 6 shows the circuit diagram of the V_(IN)-circuit 200. It includesa detection circuit 210 and a signal generation circuit 250. Thedetection circuit 210 generates a slope signal V_(SD) by detecting theslope of the current signal V_(I). The slope of the current signal V_(I)is measured in response to the oscillation signal IPS and the timingsignals S₁, S₂. The signal generation circuit 250 further receives theslope signal V_(SD) to generate the input-voltage signal V_(V) (shown inFIG. 10), the control signal ENB, the current-limit signal V_(M) and theblanking adjustment signal V_(B).

FIG. 7 is a preferred embodiment of the detection circuit 210. A firstterminal of a first capacitor 223 is coupled to receive the currentsignal V_(I) though a first switch 215. A second terminal of thecapacitor 223 is connected to the ground via a third switch 216. A firstterminal of a second capacitor 220 is coupled to receive the currentsignal V_(I) as well through a second switch 211. A second terminal ofthe second capacitor 220 is connected to the ground. The first terminalof the second capacitor 220 is further connected to the first terminalof the first capacitor 223 through a fourth switch 212. The secondswitch 211 is controlled by the second timing signal S₂. The fourthswitch 212 is controlled by the second timing signal S₂ through aninverter 214. Both switches 215 and 216 are controlled by the firsttiming signal S₁. A first terminal of a third capacitor 225 is coupledto the second terminal of the first capacitor 223 via a fifth switch219. A second terminal of the third capacitor 225 is coupled to theground. The fifth switch 219 is controlled by a pulse signal S_(P). Thepulse signal S_(P) is produced in response to the oscillation signal IPSthrough a pulse generator 230. The slope signal V_(SD) is generated onthe third capacitor 225.

The first capacitor 223 is therefore coupled to sample-and-hold thecurrent signal V_(I) through the switches 215 and 216 to generate afirst signal during the first period T₁ (shown in FIG. 9) after thepower transistor 20 (shown in FIG. 2) is turned on. The second capacitor220 is coupled to sample-and-hold the current signal V_(I) through thesecond switch 211 to generate a second signal during the second periodT₂ (shown in FIG. 9) after the power transistor 20 is turned on. Thethird capacitor 225 is coupled to sample-and-hold the differentialvoltage of the first signal and the second signal to generate the slopesignal V_(SD). The slope signal V_(SD) is thus correlated to the slopeof the current signal V_(I). The level of the slope signal V_(SD) iscorrected correlated to the input voltage V_(IN) of the power converter.The slope signal V_(SD) is increased in response to the increase of theinput voltage V_(IN).

FIG. 8 shows the schematic circuit diagram of the pulse generator 230.The pulse generator 230 comprises a constant current-source 232, atransistor 231, a capacitor 235 and an NOR gate 236 to produces thepulse signal S_(P) in response to the falling edge of the oscillationsignal IPS. The gate of the transistor 231 is coupled to receive theoscillation signal IPS. The oscillation signal IPS is used to controlthe transistor 231. The source of the transistor 231 is coupled to theground. The constant current-source 232 is coupled between the drain ofthe transistor 231 and the supply voltage V_(CC). The capacitor 235 iscoupled from the drain of the transistor 231 to the ground. The inputterminals of the NOR gate 236 are coupled to the capacitor 235 and theoscillation signal IPS respectively. The pulse signal S_(P) is generatedat the output terminal of the NOR gate 236. The constant current-source232 is used to charge the capacitor 235 when the transistor 231 isturned off in response to the falling edge of the oscillation signalIPS. The pulse signal S_(P) is enabled during charging the capacitor235. The current of the constant current-source 232 and the capacitanceof the capacitor 235 determine the pulse width of the pulse signalS_(P).

FIG. 9 shows signal-waveforms. The oscillation circuit 100 generates thetiming signals S₁ and S₂ in accordance with threshold voltages V₁ and V₂respectively (shown in the FIG. 5). The first timing signal S₁ includesthe first period T₁. The timing signal S₂ has the second period T₂. Thedetection circuit 210 samples the current signal V_(I) during the firstperiod T₁ generates the first signal (shown in the FIG. 7). Sampling thecurrent signal V_(I) during the second period T₂ generates the secondsignal. The slope signal V_(SD) is determined in accordance withdifferential voltage of the first signal and the second signal.

FIG. 10 shows the circuit diagram of the signal generation circuit 250.It includes a V_(IN) signal generator 300 and a protection signalgenerator 350. The V_(IN) signal generator 300 has an operationalamplifier 310 coupled to amplify the slope signal V_(SD) for generatingthe input-voltage signal V_(V). The positive input terminal of theoperational amplifier 310 is coupled to receive the slope signal V_(SD).A resistor 315 is coupled between the negative input terminal of theoperational amplifier 310 and the ground. A resistor 316 is coupled fromthe negative input terminal of the operational amplifier 310 to theoutput terminal of the operational amplifier 310. Resistors 315 and 316determine the gain of the amplification.

The protection signal generator 350 serves as a protection circuit tocontrol the switching signal S_(W) in response to the input-voltagesignal V_(V). The protection signal generator 350 includes comparators320, 325 and operational amplifiers 330, 340 coupled to receive theinput-voltage signal V_(V). A resistor 335 is coupled between thenegative input terminal of the operational amplifier 330 and theinput-voltage signal V_(V). A resistor 336 is coupled from the negativeinput terminal of the operational amplifier 330 to the output terminalof the operational amplifier 330. Resistors 335 and 336 determine thegain for operational amplifier 330. A resistor 345 is coupled betweenthe negative input terminal of the operational amplifier 340 and theinput-voltage signal V_(V). A resistor 346 is coupled from the negativeinput terminal of the operational amplifier 340 to the output terminalof the operational amplifier 340. Resistors 345 and 346 determine thegain for operational amplifier 340. A reference voltage V_(R) connectsthe positive input terminals of the operational amplifiers 330 and 340.

Threshold voltages V_(TH) and V_(TL) are coupled to comparators 320 and325 respectively. The over-voltage threshold V_(TH) is coupled to thepositive input terminal of the over-voltage comparator 320. The negativeinput terminal of the over-voltage comparator 320 is coupled to receivethe input-voltage signal V_(V). The over-voltage comparator 320 is usedto detect the over-voltage of the input-voltage signal V_(V). Theover-voltage comparator 320 generates an over-voltage signal when theinput-voltage signal V_(V) is higher than the over-voltage thresholdV_(TH). The under-voltage threshold V_(TL) is coupled to the negativeinput terminal of the under-voltage comparator 325. The positive inputterminal of the under-voltage comparator 325 is coupled to receive theinput-voltage signal V_(V). The under-voltage comparator 325 is used todetect the under-voltage of the input-voltage signal V_(V). Theunder-voltage comparator 325 generates an under-voltage signal when theinput-voltage signal V_(V) is lower than the under-voltage thresholdV_(TL). Input terminals of an AND gate 360 are connected to the outputterminals of the comparators 320 and 325. The output terminal of the ANDgate 360 generates the control signal ENB through a delay circuit 370.The delay circuit 370 provides a time delay for the disable of thecontrol signal ENB when the over-voltage or the under-voltage of theinput-voltage signal V_(V) is occurred.

The operational amplifier 330 serves as a current-limit adjustmentcircuit for adjusting a current limit of the transformer 30 (shown inthe FIG. 2) in response to the input-voltage signal V_(V). It is alsoadjusting the current limit of the power transistor 20 (shown in theFIG. 2). The operational amplifier 330 produces the current-limit signalV_(M) to disable the switching signal S_(W) for limiting the switchingcurrent I_(P) (shown in the FIG. 2) The operational amplifier 340 servesas a signal adjustment circuit and generates the blanking adjustmentsignal V_(B) for adjusting the blanking time of the switching signalS_(W) in response to the input-voltage signal V_(V). The current-limitsignal V_(M) is decreased in response to the increase of theinput-voltage signal V_(V). The blanking adjustment signal V_(B) isincreased in response to the decrease of the input-voltage signal V_(V).

FIG. 11 shows a circuit schematic of the blanking circuit 80. Theblanking circuit 80 comprises a constant current-source 85, a transistor82, a capacitor 83, a comparator 87, an inverter 81 and an NAND gate 89to produce the blanking signal S_(K) in response to the rising edge ofthe switching signal S_(W). The constant current-source 85 is coupledfrom the supply voltage V_(CC) to the drain of the transistor 82. Thegate and the source of the transistor 82 are coupled to the outputterminal of the inverter 81 and the ground respectively. The capacitor83 is coupled between the drain of the transistor 82 and the ground. Theswitching signal S_(W) is coupled to the input terminal of the inverter81 to control the transistor 82 through the inverter 81. Therefore theconstant current source 85 will start to charge the capacitor 83 oncethe switching signal S_(W) is turned on.

The capacitor 83 is connected to the negative input terminal of thecomparator 87 to compare with the blanking adjustment signal V_(B)coupled to the positive input terminal of the comparator 87. The outputterminal of the comparator 87 is connected to the input terminal of theNAND gate 89. Another input terminal of the NAND gate 89 is connected tothe switching signal S_(W). The blanking signal S_(K) is thus generatedat the output terminal of the NAND gate 89. The current of the constantcurrent-source 85, the capacitance of the capacitor 83 and level of theblanking adjustment signal V_(B) determine the blanking time of theblanking signal S_(K). The blanking time of the blanking signal S_(K) istherefore increased in response to the decrease of the input voltageV_(IN).

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncovers modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A control circuit of a power converter including an input voltagedetection, comprising: a power transistor coupled to a transformer forswitching the transformer; a current sense circuit generating a currentsignal in response to a switching current of the transformer; aswitching circuit coupled to receive the current signal and a feedbacksignal to generate a switching signal for controlling the powertransistor and regulating the output of the power converter; a detectioncircuit coupled to sense the current signal for generating a slopesignal in accordance with a slope of the current signal; a signalgenerator generating an input-voltage signal in accordance with theslope signal; and a protection circuit coupled to control the switchingsignal in response to the input-voltage signal; wherein theinput-voltage signal is corrected correlated to the input voltage of thepower converter.
 2. the control circuit as claimed in claim 1, whereinthe slope of the current signal is detected when the power transistor isturned on.
 3. The control circuit as claimed in claim 1, wherein a firstsignal is generated by the detection circuit sampling the current signalduring a first period when the power transistor is turned on, a secondsignal is generated by the detection circuit sampling the current signalduring a second period when the power transistor is turned on, the slopeof the current signal is determined in accordance with the first signaland the second signal.
 4. The control circuit as claimed in claim 1,wherein the detection circuit comprises: a first capacitor coupled tosample-and-hold the current signal through a first switch during a firstperiod after the power transistor is turned on; a second capacitorcoupled to sample-and-hold the current signal through a second switchduring a second period after the power transistor is turned on; and athird capacitor coupled to sample-and-hold the differential voltage ofthe first capacitor and the second capacitor for generating the slopesignal.
 5. The control circuit as claimed in claim 4, wherein the firstswitch is controlled by a first sample signal, the second switch iscontrolled by a second sample signal, the first sample signal and thesecond sample signal are generated by an oscillation circuit of thepower converter.
 6. The control circuit as claimed in claim 5, whereinthe oscillation circuit further generates an oscillation signal coupledto enable the power transistor, the first sample signal and the secondsample signal are synchronized with the oscillation signal.
 7. Thecontrol circuit as claimed in claim 1, wherein the signal generatorcomprises: an operational amplifier coupled to amplify the slope signalfor generating the input-voltage signal.
 8. The control circuit asclaimed in claim 1, wherein the protection circuit comprises: anover-voltage comparator coupled to receive the input-voltage signal andan over-voltage threshold to generate an over-voltage signal when theinput-voltage signal is higher than the over-voltage threshold; whereinthe over-voltage signal is coupled to disable the switching signal. 9.The control circuit as claimed in claim 1, wherein the protectioncircuit comprises: an under-voltage comparator coupled to receive theinput-voltage signal and an under-voltage threshold to generate anunder-voltage signal when the input-voltage signal is lower than theunder-voltage threshold; wherein the under-voltage signal is coupled todisable the switching signal.
 10. The control circuit as claimed inclaim 1, wherein the protection circuit comprises: a current-limitadjustment circuit coupled to receive the input-voltage signal togenerate a current limit signal to disable the switching signal forlimiting the switching current of the power converter; wherein thecurrent limit signal is decreased in response to the increase of theinput voltage of the power converter.
 11. The control circuit as claimedin claim 1, wherein the protection circuit comprises: a signaladjustment circuit coupled to receive the input-voltage signal togenerate a blanking adjustment signal for adjusting a blanking time ofthe switching signal; wherein the blanking time is increased in responseto the decrease of the input voltage of the power converter.
 12. Acontrol circuit of a power converter including an input voltagedetection, comprising: a power transistor coupled to a transformer forswitching the transformer; a current sense circuit generating a currentsignal in response to a switching current of the transformer; aswitching circuit coupled to receive the current signal and a feedbacksignal to generate a switching signal for controlling the powertransistor and regulating the output of the power converter; a detectioncircuit coupled to sense the current signal for generating a slopesignal; and a protection circuit coupled to control the switching signalin response to the slope signal; wherein the level of the slope signalis corrected correlated to the input voltage of the power converter. 13.The control circuit as claimed in claim 12, wherein the slope signal iscorrelated to a slope of the switching current.
 14. The control circuitas claimed in claim 12, wherein a first signal is generated by thedetection circuit sampling the current signal during a first period whenthe power transistor is turned on, a second signal is generated by thedetection circuit sampling the current signal during a second periodwhen the power transistor is turned on, the slope signal is generated inaccordance with the first signal and the second signal.
 15. The controlcircuit as claimed in claim 12, wherein the detection circuit comprises:a first capacitor coupled to sample-and-hold the current signal througha first switch during a first period after the power transistor isturned on; a second capacitor coupled to sample-and-hold the currentsignal through a second switch during a second period after the powertransistor is turned on; and a third capacitor coupled tosample-and-hold the differential voltage of the first capacitor and thesecond capacitor for generating the slope signal; wherein the slopesignal is correlated to a slope of the current signal.
 16. The controlcircuit as claimed in claim 12, wherein the protection circuitcomprises: an over-voltage comparator generating an over-voltage signalin response to the slope signal and an over-voltage threshold when theslope signal is higher than the over-voltage threshold; wherein theover-voltage signal is coupled to disable the switching signal.
 17. Thecontrol circuit as claimed in claim 12, wherein the protection circuitcomprises: an under-voltage comparator generating an under-voltagesignal in response to the slope signal and an under-voltage thresholdwhen the slope signal is lower than the under-voltage threshold; whereinthe under-voltage signal is coupled to disable the switching signal. 18.The control circuit as claimed in claim 12, wherein the protectioncircuit comprises: a current-limit adjustment circuit generating acurrent limit signal to disable the switching signal for limiting theswitching current of the power converter in response to the slopesignal; wherein the current limit signal is decreased in response to theincrease of the input voltage of the power converter.
 19. The controlcircuit as claimed in claim 12, wherein the protection circuitcomprises: a signal adjustment circuit generating a blanking adjustmentsignal for adjusting a blanking time of the switching signal in responseto the slope signal; wherein the blanking time is increased in responseto the decrease of the input voltage of the power converter.
 20. Acontrol circuit of a power converter, comprising: a switching circuitgenerating a switching signal for controlling a power transistor andregulating the output of the power converter in response to a switchingcurrent and a feedback signal; a detection circuit coupled to sense theswitching current for generating a slope signal; and a protectioncircuit coupled to control the switching signal in response to the slopesignal; wherein the slope signal is corrected correlated to an inputvoltage of the power converter.
 21. The control circuit as claimed inclaim 20, wherein the slope signal is correlated to a slope of theswitching current.
 22. The control circuit as claimed in claim 20,wherein a first signal is generated by the detection circuit samplingthe switching current during a first period when the power transistor isturned on, a second signal is generated by the detection circuitsampling the switching current during a second period when the powertransistor is turned on, the slope signal is generated in accordancewith the first signal and the second signal.
 23. The control circuit asclaimed in claim 20, wherein the detection circuit comprises: a firstcapacitor coupled to sample-and-hold the switching current through afirst switch during a first period after the power transistor is turnedon; a second capacitor coupled to sample-and-hold the switching currentthrough a second switch during a second period after the powertransistor is turned on; and a third capacitor coupled tosample-and-hold the differential voltage of the first capacitor and thesecond capacitor for generating the slope signal; wherein the slopesignal is correlated to a slope of the switching current.
 24. Thecontrol circuit as claimed in claim 20, wherein the protection circuitcomprises: a current-limit adjustment circuit adjusting a current limitof the power transistor in response to the slope signal.
 25. The controlcircuit as claimed in claim 24, wherein the current-limit adjustmentcircuit generates a current limit signal to disable the switching signalfor the current limit in response to the slope signal, the current limitsignal is decreased in response to the increase of the input voltage ofthe power converter.
 26. The control circuit as claimed in claim 20,wherein the protection circuit comprises: an over-voltage comparatorgenerating an over-voltage signal in response to the slope signal and anover-voltage threshold when the slope signal is higher than theover-voltage threshold; wherein the over-voltage signal is coupled todisable the switching signal.
 27. The control circuit as claimed inclaim 20, wherein the protection circuit comprises: an under-voltagecomparator generating an under-voltage signal in response to the slopesignal and an under-voltage threshold when the slope signal is lowerthan the under-voltage threshold; wherein the under-voltage signal iscoupled to disable the switching signal.
 28. The control circuit asclaimed in claim 20, wherein the protection circuit comprises: a signaladjustment circuit generating a blanking adjustment signal for adjustinga blanking time of the switching signal in response to the slope signal;wherein the blanking time is increased in response to the decrease ofthe input voltage of the power converter.
 29. A control method of apower converter, comprising: generating a switching signal forcontrolling a power transistor in response to a switching current;sensing a slope of the switching current for generating a slope signalcorrected correlated to an input voltage of the power converter; andcontrolling the switching signal in response to the slope signal. 30.The control method as claimed in claim 29, wherein generating aswitching signal further comprises for regulating the output of thepower converter in response to a feedback signal.
 31. The control methodas claimed in claim 29, wherein the step of sensing a slope of theswitching current for generating a slope signal comprises: generating afirst signal in response to the switching current during a first periodwhen the power transistor is turned on; generating a second signal inresponse to the switching current during a second period when the powertransistor is turned on; and generating the slope signal correlated tothe slope of the switching current in accordance with the first signaland the second signal.
 32. The control method as claimed in claim 29,wherein the step of controlling the switching signal comprises:generating an over-voltage signal to disable the switching signal inresponse to the slope signal and an over-voltage threshold when theslope signal is higher than the over-voltage threshold.
 33. The controlmethod as claimed in claim 29, wherein the step of controlling theswitching signal comprises: generating an under-voltage signal todisable the switching signal in response to the slope signal and anunder-voltage threshold when the slope signal is lower than theunder-voltage threshold.
 34. The control method as claimed in claim 29,wherein the step of controlling the switching signal comprises:generating a blanking adjustment signal for adjusting a blanking time ofthe switching signal in response to the slope signal.
 35. The controlmethod as claimed in claim 34, wherein the blanking time is increased inresponse to the decrease of the input voltage of the power converter.36. The control method as claimed in claim 29, wherein the step ofcontrolling the switching signal comprises: adjusting a current limit ofthe power transistor in response to the slope signal.